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Espressif Systems /ESP32-S2 /PMS /APB_PERIPHERAL_INTR

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Interpret as APB_PERIPHERAL_INTR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (APB_PERI_BYTE_ERROR_CLR)APB_PERI_BYTE_ERROR_CLR 0 (APB_PERI_BYTE_ERROR_EN)APB_PERI_BYTE_ERROR_EN 0 (APB_PERI_BYTE_ERROR_INTR)APB_PERI_BYTE_ERROR_INTR

Description

PeribBus2 permission control register.

Fields

APB_PERI_BYTE_ERROR_CLR

The clear signal for APB peripheral interrupt.
APB_PERI_BYTE_ERROR_EN

The enable signal for APB peripheral access interrupt.
APB_PERI_BYTE_ERROR_INTR

APB peripheral access interrupt signal.

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data